An efficient prediction framework for multi-parametric yield analysis under parameter variations

Abstract

Due to continuous process scaling, process, voltage, and temperature (PVT) parameter variations have become one of the most problematic issues in circuit design. The resulting correlations among performance metrics lead to a significant para-metric yield loss. Previous algorithms on parametric yield prediction are limited to predicting a single-parametric yield or per-forming balanced optimization for several single-parametric yields. Consequently, these methods fail to predict the multi- parametric yield that optimizes multiple performance metrics simultaneously, which may result in significant accuracy loss. In this paper we suggest an efficient multi-parametric yield prediction framework, in which multiple performance metrics are considered as simultaneous constraint conditions for parametric yield prediction, to maintain the correlations among metrics. First, the framework models the performance metrics in terms of PVT parameter variations by using the adaptive elastic net (AEN) method. Then the parametric yield for a single performance metric can be predicted through the computation of the cumulative distribution function (CDF) based on the multiplication theorem and the Markov chain Monte Carlo (MCMC) method. Finally, a copula-based parametric yield prediction procedure has been developed to solve the multi-parametric yield prediction problem, and to generate an accurate yield estimate. Experimental results demonstrate that the proposed multi-parametric yield prediction framework is able to provide the designer with either an accurate value for parametric yield under specific performance limits, or a multi-parametric yield surface under all ranges of performance limits.

Keywords

Yield prediction / Parameter variations / Multi-parametric yield / Performance modeling / Sparse representation

References

[1] Banerjee, A., Chatterjee, A., 2015. Signature driven hierar-chical post-manufacture tuning of RF systems for per-formance and power. IEEE Trans. VLSI Syst., 23(2):342–355. http://dx.doi.org/10.1109/TVLSI.2014.2309114

[2] Bayrakci, A.A., 2015. Stochastic logical effort as a variation aware delay model to estimate timing yield. Integr. VLSI J., 48(1):101–108. http://dx.doi.org/10.1016/j.vlsi.2014.07.003

[3] Binois, M., Rullière, D., Roustant, O., 2015. On the estimation of Pareto fronts from the point of view of copula theory. Inform. Sci., 324:270–285. http://dx.doi.org/10.1016/j.ins.2015.06.037

[4] Haghdad, K., Anis, M., 2012. Timing yield analysis consider-ing process-induced temperature and supply voltage variations. Microelectron. J., 43(12):956–961. http://dx.doi.org/10.1016/j.mejo.2012.07.014

[5] Houda, M., Lisser, A., 2015. Archimedean copulas in joint chance-constrained programming. Commun. Comput. Inform. Sci., 509:126–139. http://dx.doi.org/10.1007/978-3-319-17509-6_9

[6] Huang, B., Du, X., 2008. Probabilistic uncertainty analysis by mean-value first order Saddlepoint approximation. Reliab. Eng. Syst. Safety, 93(2):325–336. http://dx.doi.org/10.1016/j. ress.2006.10.021

[7] Hwang, E.J., Kim, W., Kim, Y.H., 2013. Timing yield slack for timing yield-constrained optimization and its application to statistical leakage minimization. IEEE Trans. VLSI Syst., 21(10):1783–1796. http://dx.doi.org/10.1109/TVLSI.2012.2220792

[8] Jin, Y.J., 2013. Reliability-based sensitivity analysis for ma-chining precision by saddle-point approximation. Appl. Mech. Mater., 241-244:280–283. http://dx.doi.org/10.4028/www.scientific.net/AMM.241-244.280

[9] Kaneda, S., Mizumoto, T., Maeno, T., et al., 2015. A cross validation of network system models for delay tolerant networks. Int. Conf. on Mobile Computing and Ubiqui-tous Networking, p.185–190. http://dx.doi.org/10.1109/ICMU.2015.7061064

[10] Kao, S.C., Govindaraju, R.S., 2008. Trivariate statistical analysis of extreme rainfall events via the Plackett family of copulas. Water Resources Res., 44(2):333–341. http://dx.doi.org/10.1029/2007WR006261

[11] Kim, G., Silvapulle, M.J., Silvapulle, P., 2007. Comparison of semiparametric and parametric methods for estimating copulas. Comput. Statist. Data Anal., 51(6):2836–2850. http://dx.doi.org/10.1016/j.csda.2006.10.009

[12] Kondamadugula, S., Naidu, S.R., 2016. Parameter-importance based Monte-Carlo technique for variation-aware analog yield optimization. Proc. 26th edition on Great Lakes Symp. on VLSI, p.51–56. http://dx.doi.org/10.1145/2902961.2903018

[13] Lan, W., Wang, H., Tsai, C., 2012. A Bayesian information criterion for portfolio selection. Comput. Statist. Data Anal., 56(1):88–99. http://dx.doi.org/10.1016/j.csda.2011.06.012

[14] Li, X., 2010. Finding deterministic solution from underdeter-mined equation: large-scale performance variability modeling of analog/RF circuits. IEEE Trans. Comput.- Aided Des. Integr. Circ. Syst., 29(11):1661–1668. http://dx.doi.org/10.1109/TCAD.2010.2061292

[15] Li, X., Sun, J., Xiao, F., et al., 2016. An efficient bi-objective optimization framework for statistical chip-level yield analysis under parameter variations. Front. Inform. Technol. Electron. Eng., 17(2):160–172. http://dx.doi.org/10.1631/FITEE.1500168

[16] Liu, X., Tan, S.X.D., Palma-Rodriguez, A.A., et al., 2013. Performance bound analysis of analog circuits in frequency- and time-domain considering process varia-tions. ACM Trans. Des. Autom. Electron. Syst., 19(1):6. http://dx.doi.org/10.1145/2534395

[17] Mande, S.S., Chandorkar, A.N., Iwai, H., 2013. Computation-ally efficient methodology for statistical characterization and yield estimation due to inter- and intra-die process variations. Proc. 5th Asia Symp. on Quality Electronic Design, p.287–294. http://dx.doi.org/10.1109/ASQED.2013.6643602

[18] Nateghi, H., El-Sankary, K., 2015. A self-healing technique using ZTC biasing for PVT variations compensation in 65nm CMOS technology. Canadian Conf. on Electrical and Computer Engineering, p.128–131. http://dx.doi.org/10.1109/CCECE.2015.7129173

[19] Nelson, R.B., 2006. An Introduction to Copulas. Springer, New York. http://dx.doi.org/10.1007/0-387-28678-0

[20] Panchal, G., Ganatra, A., Kosta, Y.P., et al., 2010. Searching most efficient neural network architecture using Akaike’s information criterion (AIC). Int. J. Comput. Appl., 1(5): 41–44. http://dx.doi.org/10.5120/126-242

[21] Radfar, M., Singh, J., 2014. A yield improvement technique in severe process, voltage, and temperature variations and extreme voltage scaling. Microelectron. Reliab., 54(12): 2813–2823. http://dx.doi.org/10.1016/j.microrel.2014.07.138

[22] Srivastava, A., Chopra, K., Shah, S., et al., 2008. A novel approach to perform gate-level yield analysis and opti-mization considering correlated variations in power and performance. IEEE Trans. Comput.-Aided Des. Integr. Circ. Syst., 27(2):272–285. http://dx.doi.org/10.1109/TCAD.2007.907227

[23] Sun, J., Li, J., Ma, D., et al., 2008. Chebyshev affine- arithmetic-based parametric yield prediction under lim-ited descriptions of uncertainty. IEEE Trans. Comput.- Aided Des. Integr. Circ. Syst., 27(10):1852–1865. http://dx.doi.org/10.1109/TCAD.2008.2003300

[24] Tang, A., Jha, N.K., 2016. GenFin: genetic algorithm-based multiobjective statistical logic circuit optimization using incremental statistical analysis. IEEE Trans. VLSI Syst., 24(3):1126–1139. http://dx.doi.org/10.1109/TVLSI.2015.2442260

[25] Tlelo-Cuautle, E., Sanabria-Borbon, A.C., 2016. Optimising operational amplifiers by evolutionary algorithms and gm/Id method. Int. J. Electron., 103(10):1665–1684. http://dx.doi.org/10.1080/00207217.2016.1138522

[26] Trejo-Guerra, R., Tlelo-Cuautle, E., Jiménez-Fuentes, J.M., et al., 2012. Integrated circuit generating 3- and 5-scroll attractors. Commun. Nonl. Sci. Numer. Simul., 17(11): 4328–4335. http://dx.doi.org/10.1016/j.cnsns.2012.01.029

[27] Visweswariah, C., 2003. Death, taxes and failing chips. Proc. 40th Annual Design Automation Conf., p.343–347. http://dx.doi.org/10.1145/775919.775921

[28] Wang, D., Hutson, A.D., 2015. Inversion theorem based kernel density estimation for the ordinary least squares estimator of a regression coefficient. Commun. Statist. Theory Methods, 44(8):1571–1579. http://dx.doi.org/10.1080/03610926.2013.781633

[29] Xu, F., Li, C., Jiang, T., 2015. Printed circuit board model updating based on response surface method. J. Beijing Univ. Aeronaut. Astronaut., 41(3):449–455 (in Chinese).

[30] Yuan, X., 2009. Application Research of Markov Chain Sim-ulation in Reliability Analysis. PhD Thesis, Northwestern Polytechnical University, Xi’an, China (in Chinese).

[31] Yuan, X.K., Lu, Z.Z., Qiao, H.W., 2010. Conditional proba-bility Markov chain simulation based reliability analysis method for nonnormal variables. Sci. China Technol. Sci., 53(5):1434–1441. http://dx.doi.org/10.1007/ s11431-010-0138-9

[32] Zhang, H., Zamar, R.H., 2014. Least angle regression for model selection. Wiley Interdiscipl. Rev. Comput. Statist., 6(2):116–123. http://dx.doi.org/10.1002/wics.1288

[33] Zou, H., 2006. The adaptive Lasso and its Oracle properties. J. Am. Statist. Assoc., 101(476):1418–1429. http://dx.doi.org/10.1198/016214506000000735

[34] Zou, H., Zhang, H.H., 2009. On the adaptive elastic-net with a diverging number of parameters. Ann. Statist., 37(4): 1733–1751. http://dx.doi.org/10.1214/08-AOS625

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