Wide-range tracking technique for process-variation-robust clock and data recovery applications

Abstract

A wide-range tracking technique for clock and data recovery (CDR) circuit is presented. Compared to the traditional technique, a digital CDR controller with calibration is adopted to extend the tracking range. Because of the use of digital circuits in the design, CDR is not sensitive to process and power supply variations. To verify the technique, the whole CDR circuit is implemented using 65-nm CMOS technology. Measurements show that the tracking range of CDR is greater than ±6×10⁻³ at 5 Gb/s. The receiver has good jitter tolerance performance and achieves a bit error rate of<10^–12. The re-timed and re-multiplexed serial data has a root-mean-square jitter of 6.7 ps.

Keywords

Clock and data recovery / Digital loop filter / Phase interpolator

References

[1] Abiri,B., Sheikholeslami, A., Tamura,H. , , 2011. A 5Gb/s adaptive DFE for 2x blind ADC-based CDR in 65nm CMOS. IEEE Int. Solid-State Circuits Conf., p.436–438. http://dx.doi.org/10.1109/ISSCC.2011.5746386

[2] Agrawal,A., Liu,A., Hanumolu,P.K. , , 2009. An 8×5 Gb/s parallel receiver with collaborative timing recovery. IEEE J. Sol.-State Circ., 44(11):3120–3130. http://dx.doi.org/10.1109/JSSC.2009.2033399

[3] Anand,S.B., Razavi, B., 2001. A CMOS clock recovery circuit for 2.5-Gb/s NRZ data. IEEE J. Sol.-State Circ., 36(3): 432–439. http://dx.doi.org/10.1109/4.910482

[4] Coban,A.L., Koroglu, M.H., Ahmed,K.A. , 2005. A 2.5-3.125-Gb/s quad transceiver with second-order analog DLLbased CDRs. IEEE J. Sol.-State Circ., 40(9):1940–1947. http://dx.doi.org/10.1109/JSSC.2005.848142

[5] Kalantari,N., Buckwalter, J.F., 2013. A multichannel serial link receiver with dual-loop clock-and-data recovery and channel equalization. IEEE Trans. Circ. Syst. I, 60(11): 2920–2931. http://dx.doi.org/10.1109/TCSI.2013.2256172

[6] Leibowitz,B.S., Kizer, J., Lee,H. , , 2007. A 7.5 Gb/s 10-tap DFE receiver with first tap partial response, spectrally gated adaptation, and 2nd-order data-filtered CDR. IEEE Int. Solid-State Circuits Conf., p.228–599. http://dx.doi.org/10.1109/ISSCC.2007.373377

[7] Nikolic,B., Oklobdzija, V.G., Stojanovic,V. , , 2000. Improved sense-amplifier-based flip-flop: design and measurements. IEEE J. Sol.-State Circ., 35(6):876–884. http://dx.doi.org/10.1109/4.845191

[8] Niu,Y., Wu,L.J., Liu,Y., , 2013. A 10 Gbps in-line network security processor based on configurable heteromulti-cores. J. Zhejiang Univ.-Sci. C (Comput. & Electron.), 14(8):642–651. http://dx.doi.org/10.1631/jzus.C1200370

[9] Razavi,B., 2003. Designing bangbang PLLs for clock and data recovery in serial data transmission systems. In: Razavi, B. (Ed.), Phase-Locking in High-Performance Systems: from Devices to Architectures. Wiley-IEEE Press, p.34–45. http://dx.doi.org/10.1109/9780470545492.ch4

[10] Sarvari,S., Tahmoureszadeh, T., Sheikholeslami,A. , , 2010. A 5 Gb/s speculative DFE for 2× blind ADC-based receivers in 65-nm CMOS. IEEE Symp. on VLSI Circuits, p.69–70. http://dx.doi.org/10.1109/VLSIC.2010.5560273

[11] Sidiropoulos,S., Horowitz, M., 1997. A semidigital dual delay-locked loop. IEEE J. Sol.-State Circ., 32(11):1683–1692. http://dx.doi.org/10.1109/4.641688

[12] Tamura,H., Kibune, M., Takahashi,Y. , , 2001. 5 Gb/s bidirectional balanced-line link compliant with plesiochronous clocking. IEEE Int. Solid-State Circuits Conf., p.64–65. http://dx.doi.org/10.1109/ISSCC.2001.912547

[13] Weinlader,D.K., 2001. Precision CMOS Receivers for VLSI Testing Application. PhD Thesis, Stanford University, USA. http://chipgen.stanford.edu/people/alum/pdf/0111_Weinl ader_Precision_CMOS_Receivers_.pdf

[14] Yang,X.B., Chi,B.Y., Wei,M., , 2013. A half-rate CDR with DCD cleaning up and quadrature clock calibration for 20 Gbps 60 GHz communication in 65 nm CMOS. IEEE Int. Symp. on Circuits and Systems, p.962–965. http://dx.doi.org/10.1109/ISCAS.2013.6572008

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2017 Zhejiang University and Springer-Verlag Berlin Heidelberg