ApipelinedReed-Solomon decoder based on a modified step-by-step algorithm

Xing-ru PENG, Wei ZHANG, Yan-yan LIU

PDF(425 KB)
PDF(425 KB)
Front. Inform. Technol. Electron. Eng ›› 2016, Vol. 17 ›› Issue (9) : 954-961. DOI: 10.1631/FITEE.1500303
Article
Article

ApipelinedReed-Solomon decoder based on a modified step-by-step algorithm

Author information +
History +

Abstract

We propose a pipelined Reed-Solomon (RS) decoder for an ultra-wideband system using a modified stepby-step algorithm. To reduce the complexity, the modified step-by-step algorithm merges two cases of the original algorithm. The pipelined structure allows the decoder to work at high rates with minimum delay. Consequently, for RS(23,17) codes, the proposed architecture requires 42.5% and 24.4% less area compared with a modified Euclidean architecture and a pipelined degree-computationless modified Euclidean architecture, respectively. The area of the proposed decoder is 11.3% less than that of the previous step-by-step decoder with a lower critical path delay.

Keywords

Reed-Solomon codes / Step-by-step algorithm / Ultra-wideband / Pipelined structure

Cite this article

Download citation ▾
Xing-ru PENG, Wei ZHANG, Yan-yan LIU. ApipelinedReed-Solomon decoder based on a modified step-by-step algorithm. Front. Inform. Technol. Electron. Eng, 2016, 17(9): 954‒961 https://doi.org/10.1631/FITEE.1500303

References

[1]
Baek, J.H., Sunwoo, M.H., 2006. New degree computationless modified Euclid algorithm and architecture for Reed-Solomon decoder. IEEE Trans. VLSI Syst., 14(8):915–920. http://dx.doi.org/10.1109/TVLSI.2006.878484
[2]
Batra, A., Balakrishnan, J., Dabak, A., , 2004. Multiband OFDM Physical Layer Proposal for IEEE 802.15 Task Group 3a. IEEE P802.15-03/268r2.
[3]
Berlekamp, E.R., 1968. Algebraic Coding Theory. McGraw-Hill, New York.
[4]
Chen, T.C., Tasi, M.H., 2007. Hardware implementation of a high-speed (32, 24, 4) RS decoder. Chung Hua J. Sci. Eng., 5(4):21–27.
[5]
Chen, T.C., Wei, C.H., Wei, S.W., 2000. Step-by-step decoding algorithm for Reed-Solomon codes. IEE Proc. Commun., 147(1):8–12. http://dx.doi.org/10.1049/ip-com:20000149
[6]
Chen, T.C., Wei, C.H., Wei, S.W., 2003. A pipeline structure for high-speed step-by-step RS decoding.IEICE Trans. Commun., E86-B(2):847–849.
[7]
Das, A.S., Das, S., Bhaumik, J., 2013. Design of RS(255,251) encoder and decoder in FPGA. Int. J. Soft Comput. Eng., 2(6):391–394.
[8]
García-Herrero, F., Valls, J., Meher, P.K., 2011. High-speed RS(255, 239) decoder based on LCC decoding. Circ. Syst. Signal Process., 30(6):1643–1669. http://dx.doi.org/10.1007/s00034-011-9327-4
[9]
Guo, W., Gai, W., 2014. Area-efficient recursive degree computationless modified Euclid’s architecture for Reed-Solomon decoder. Proc. IEEE Int. Conf. on Electron Devices and Solid-State Circuits, p.1–2. http://dx.doi.org/10.1109/EDSSC.2014.7061134
[10]
Lee, H., 2003. High-speed VLSI architecture for parallel Reed-Solomon decoder. IEEE Trans. VLSI Syst., 11(2):288–294. http://dx.doi.org/10.1109/TVLSI.2003.810782
[11]
Lee, S., Lee, H., 2008. A high-speed pipelined degreecomputationless modified Euclidean algorithm architecture for Reed-Solomon decoders. IEICE Trans. Fundament. Electron. Commun. Comput. Sci., E91-A(3):830–835.
[12]
Liu, X., Lu, C., Cheng, T.H., , 2007. A simplified step-by-step decoding algorithm for parallel decoding of Reed-Solomon codes.IEEE Trans. Commun., 55(6):1103–1109. http://dx.doi.org/10.1109/TCOMM.2007.898703
[13]
Massey, J., 1965. Step-by-step decoding of the Bose-Chaudhuri-Hocquenghem codes. IEEE Trans. Inform. Theory, 11(4):580–585. http://dx.doi.org/10.1109/TIT.1965.1053833
[14]
Sarwate, D.V., Shanbhag, N.R., 2001. High-speed architectures for Reed-Solomon decoders. IEEE Trans. VLSI Syst., 9(5):641–655. http://dx.doi.org/10.1109/92.953498
[15]
Wu, Y., 2015. New scalable decoder architectures for Reed-Solomon codes.IEEE Trans. Commun., 63(8):2741–2761. http://dx.doi.org/10.1109/TCOMM.2015.2445759
[16]
Zhang, X., Zhu, J., 2010. High-throughput interpolation architecture for algebraic soft-decision Reed-Solomon decoding. IEEE Trans. Circ. Syst. I, 57(3):581–591. http://dx.doi.org/10.1109/TCSI.2009.2023935
[17]
Zhu, J., Zhang, X., Wang, Z., 2009. Backward interpolation architecture for algebraic soft-decision Reed-Solomon decoding. IEEE Trans. VLSI Syst., 17(11):1602–1615. http://dx.doi.org/10.1109/TVLSI.2008.2005575

RIGHTS & PERMISSIONS

2016 Zhejiang University and Springer-Verlag Berlin Heidelberg
PDF(425 KB)

Accesses

Citations

Detail

Sections
Recommended

/