Design and simulation of a standing wave oscillator based PLL

Abstract

A standing wave oscillator (SWO) is a perfect clock source which can be used to produce a high frequency clock signal with a low skew and high reliability. However, it is difficult to tune the SWO in a wide range of frequencies. We introduce a frequency tunable SWO which uses an inversion mode metal-oxide-semiconductor (IMOS) field-effect transistor as a varactor, and give the simulation results of the frequency tuning range and power dissipation. Based on the frequency tunable SWO, a new phase locked loop (PLL) architecture is presented. This PLL can be used not only as a clock source, but also as a clock distribution network to provide high quality clock signals. The PLL achieves an approximately 50% frequency tuning range when designed in Global Foundry 65 nm 1P9M complementary metal-oxide-semiconductor (CMOS) technology, and can be used directly in a high performance multi-core microprocessor.

Keywords

Standing wave oscillator (SWO) / Clock distribution / Phase locked loop (PLL) / Varactor

References

[1] Andress, W., Ham, D., 2004. Recent developments in standing-wave oscillator design: review. Radio Frequency Integrated Circuits Symp., p.119–122. http://dx.<?Pub Caret?>doi.org/10.1109/RFIC.2004.1320545

[2] Andress, W., Ham, D., 2005. Standing wave oscillators utilizing wave-adaptive tapered transmission lines. IEEE J. Sol.-State Circ., 40(3):638–651. http://dx.doi.org/10.1109/JSSC.2005.843600

[3] Chan, S.C., Shepard, K.L., Restle, P.J., 2003. Design of resonant global clock distributions. 21st Int. Conf. on Computer Design, p.248–253. http://dx.doi.org/10.1109/ICCD.2003.1240902

[4] Chan, S.C., Restle, P.J., Shepard, K.L., , 2004. A 4.6 GHz resonant global clock distribution network. IEEE Int. Solid-State Circuits Conf., p.342–343. http://dx.doi.org/10.1109/ISSCC.2004.1332734

[5] Cordero, V.H., Khatri, S.P., 2008. Clock distribution scheme using coplanar transmission lines. Design, Automation and Test in Europe, p.985–990. http://dx.doi.org/10.1109/DATE.2008.4484809

[6] Drake, A.J., Nowka, K.J., Nguyen, T.Y., , 2004. Resonant clocking using distributed parasitic capacitance. IEEE J. Sol.-State Circ., 39(9):1520–1528. http://dx.doi.org/10.1109/JSSC.2004.831435

[7] Mandal, A., Karkala, V., Khatri, S.P., , 2011. Interconnected tile standing wave resonant oscillator based clock distribution circuits. 24th Int. Conf. on VLSI Design, p.82–87. http://dx.doi.org/10.1109/VLSID.2011.70

[8] O’Mahony, F., 2003. 10 GHz Global Clock Distribution Using Coupled Standing-Wave Oscillators. PhD Thesis, Stanford University, USA.

[9] O’Mahony, F., Yue, C.P., Horowitz, M.A., , 2003. A 10-GHz global clock distribution using coupled standing-wave oscillators. IEEE J. Sol.-State Circ., 38(11):1813–1820. http://dx.doi.org/10.1109/JSSC.2003.818299

[10] Wood, J., Edwards, T.C., Lipa, S., 2001. Rotary travelingwave oscillator arrays: a new clock technology. IEEE J. Sol.-State Circ., 36(11):1654–1665. http://dx.doi.org/10.1109/4.962285