Ge-on-SOI coupling structure can be used widely in large scale integrated circuits [
20]. A layer of Ge material is epitaxially grown on the SOI substrate, and a set of different sizes of active devices and passive waveguides can be fabricated through etching process. However, the current etching technology for Ge material is not mature enough. Etching the Ge waveguide will not only result in a large sidewall roughness, but also cause the inclination in the waveguide sidewall, and hence has the difficulty in keeping the steepness of the sidewall. Additionally, the etching depth is usually slightly larger than the thickness of the Ge material layer. Consequently, the surface smoothness of the underlying Si layer is spoiled, causing the increase of transmission loss of the passive waveguide beneath the active Ge waveguide. Taking into account the above shortcomings in etching the Ge waveguide, we scuttle away from the etching process in the fabrication of Ge waveguide. Instead, a mold for the coupling structure is first formed in the photoresist and then the Ge material is sputtered into the mold. With this method, the perfect surface of the Si waveguide will not be damaged. The mature inductively coupled plasma (ICP) etching is only employed to fabricate the Si waveguide [
21,
22], the vertical and mirror-liked sidewall of the passive Si waveguide can be conveniently obtained. The complete fabrication process for Ge-on-SOI coupling structure is given in detail as follows (see Fig. 9).