Frontiers of Electrical and Electronic Engineering >

2007 , Vol. 2 >Issue 1: 88 - 91

DOI: https://doi.org/10.1007/s11460-007-0016-9

Analytical delay models for RLC interconnects under ramp input

Expand
  • Department of Electronic Engineering, Shanghai Jiao Tong University, Shanghai 200030, China;

Published date: 05 Mar 2007

Fold

Abstract

Analytical delay models for Resistance Inductance Capacitance (RLC) interconnects with ramp input are presented for different situations, which include overdamped, underdamped and critical response cases. The errors of delay estimation using the analytical models proposed in this paper are less by 3% in comparison to the SPICE-computed delay. These models are meaningful for the delay analysis of actual circuits in which the input signal is ramp but not ideal step input.

Cite this article

REN Yinglei, MAO Junfa, LI Xiaochun . Analytical delay models for RLC interconnects under ramp input[J]. Frontiers of Electrical and Electronic Engineering, 2007 , 2(1) : 88 -91 . DOI: 10.1007/s11460-007-0016-9

Options
Outlines

/

〈 〉