Two-step gate-recess process combining selective wet-etching and digital wet-etching for InAlAs/InGaAs InP-based HEMTs

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Front. Inform. Technol. Electron. Eng ›› 2017, Vol. 18 ›› Issue (8) : 1180-1185. DOI: 10.1631/FITEE.1601121
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Two-step gate-recess process combining selective wet-etching and digital wet-etching for InAlAs/InGaAs InP-based HEMTs

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{{article.zuoZheEn_L}}. {{article.titleEn}}. Front. Inform. Technol. Electron. Eng, 2017, 18(8): 1180‒1185 https://doi.org/10.1631/FITEE.1601121

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